In many integrated circuit (IC) technologies, NMOS and PMOS transistors have n+ and p+ implantations placed within n-wells or p-wells or on top of a bulk p-type substrate. Having an NMOS and a PMOS device in close proximity to each other, however, can potentially form a parasitic silicon controlled rectifier (SCR), also referred to as parasitic thyristor structure.
Under normal operating conditions, the parasitic SCR is in a high-ohmic state, because the parasitic SCR has a trigger or turn-on voltage that is higher than a normal operating voltage used in standard CMOS/bipolar applications. While in the high-ohmic state, the SCR has a high impedance, typically in the Mega-Ohm region. The residual current flowing between supply (VDD) and ground (VSS) connected to the terminals of the SCR structure is the leakage current of the reverse biased p-n junction. If, however, a large transient occurs on the power supply lines, ground lines or I/O lines that exceeds the turn-on voltage or current of the parasitic SCR, the SCR may trigger.
After the SCR is triggered, the resistance of the parasitic SCR structure between power supply and ground may change to a low ohmic path, typically in the range of one Ohm to several Ohms. This short circuit may cause the integrated circuit (IC) to malfunction as a consequence of voltage break-down on the supply, or cause irreversible damage due to heat dissipation in the triggered thyristor. This phenomenon of the unintentional triggering is commonly referred to as latch-up.
Latch-up is an omnipresent risk in the modern complex integrated circuits (ICs). Contemporary ICs contain millions of transistors, placed in various blocks, such as analog blocks, IO cells, memory blocks, and logic blocks. These various blocks can have different functionalities, topologies, connectivity, supply voltages and physical structure. Due to enormously complex and diverse topology of the IC, there is a likelihood that a parasitic SCR will be unintentionally formed.